DESIGN AND OPTIMIZATION OF 14nm 7-FIN SOI FINFET by Gurleen Kaur
Scaling of standard CMOS is becoming difficult due to rising subthreshold leakage and gate leakage.
FinFETs i.e. Multi-gate FETs have come out as the most assuring contenders to extend the scaling of
CMOS insub-25nm region this is because of more electrostatic control due to use of multiple gatesover the channel which lowers the coupling between drain and source in the subthreshold regime. Both bulk and SOI FinFETs are capable of attaining similar performance. Bulk FinFETs need more convoluted doping implementation. Variability control is complex in bulk FinFETs. Dielectric isolation in SOI FinFETs results in reduced leakage current and parasitic capacitances. Sharper subthreshold slope, lower mobility degradation and smaller body effect can be achieved with SOI MOSFETs when operated in full depletion mode. Driving capability for small voltage designs can be increased by use of SOI FinFETs. This results in diminished threshold voltage roll off, reliable narrow junctions, absolute removal of latch up problems. In this thesis work, 14nm 7-fin SOI FinFET is designed and analysed using Visual TCAD. And it’s V-I characteristics are obtained and also Ion , Ioff , Ion /Ioff ratio, SS and Vth is calculated from that. And Ion /Ioff ratio is optimized w.r.t. Temperature and Oxide thickness variation using PSO.