HDL IMPLEMENTATION AND ASIC DESIGN OF 4096-POINT RADIX-2 FFT IN 0.18μM CMOS TECHNOLOGY by Pulkit Jain
Abstract
In Digital Signal Processing (DSP), Fast Fourier Transform (FFT) algorithm and its hardware implementation play a significant role. To implement FFT in hardware, fixed point arithmetic is preferred over floating point as it is simple to execute and also saves area and power. This thesis presents HDL implementation and ASIC design of 4096-point Radix-2 FFT using fixed-point arithmetic targeted for upcoming Orthogonal Frequency Division Multiplexing (OFDM) based upcoming communication and wireless and applications. The finite bit representation of signals and coefficients in fixed point result in quantization error which degrades FFT performance. This thesis presents a standard and a modified radix-2 DIT butterfly to evaluate quantization noise effects in terms of Signal to Quantization Noise Ratio (SQNR). The VHDL code has been designed and simulated using Questa-Sim and verified by designing MATLAB models. The synthesis and simulation results have been presented and compared with the standard version of the design followed by Application Specific Integrated Circuit (ASIC) design in 0.18 μm CMOS Technology. The required frontend design has been carried out by using Synopsis-Design Compiler and backend design by using Synopsis– IC Compiler. Finally design of some major blocks of radix-4 architecture has been carried out.
